Field of the Invention
The present invention relates to a multiple address holding memory apparatus which is shared by a plurality of processes or a plurality of processors, and more particularly, to a multiple address holding memory apparatus in which when data are to be stored in or read from a main memory part through random accessing, addresses at which the main memory part is to be accessed are held in advance for the purpose of efficient accessing and an order of addresses is permuted for the purpose of efficient accessing.
Description of the Background Art
Where a plurality of processes or a plurality of processors share one dynamic random access memory (hereinafter referred to as a "DRAM"), when the DRAM is to be accessed, in order to shorten an access time of accessing the DRAM, a main memory part may be internally formed as a multi bank system as customarily done in a synchronous DRAM, for example, so that an apparent access time is reduced by accessing while switching banks.
Among memory systems having such a multi bank system, and particularly among those which allow to access through an address bus and a data bus independently of each other, some memory systems adopt a method which requires accumulating addresses in an FIFO memory and supplying addresses from the FIFO memory to memory means in the input order so that it is not necessary to wait for a previous access to complete when an address bus is to be accessed. Such a memory system is disclosed in Japanese Patent Application Laid-Open Gazette No. 4-175943.
However, since a conventional memory system as described above requires accumulating addresses in an FIFO memory, information accumulated in the FIFO memory can not be retrieved in an order but for an access order in which processes or processors accessed, and therefore, address information stored in the FIFO memory an control information which is used for accessing memory means cannot be retrieved unless in the access order. This makes it impossible to re-arrange access priority ranks considering an address structured, a bank structure and the like of the memory means of the memory system which is accessed by the processes or processors and considering priority ranks of the processes or processors for accessing the memory system, for the purpose of optimum accessing, or in order words, for the purpose of accessing in such an order which minimizes an access time.
Now, an optimum access order will be described. For example, when data of different banks from each other are to be accessed continuously, it is not necessary to precharge between access of continuous data. Meanwhile, even when data of the same bank are to be accessed continuously, if data whose row addresses are the same but column addressed alone are different are to be accessed continuously, it is not necessary to precharge between accesses of continuous data in that bank.
From the above, it is considered that a reduction in an access time is possible, if an access order for accessing addresses which are planned to be accessed is changed in such a manner that addresses of different banks become continuous to each other or addresses with the same row addresses with each other become continuous to each other in the same bank, and consequently, as few precharge cycles as possible are inserted between accesses of continuous data.
However, if an access order for accessing addressed which are planned to be accessed is configured so as to be chargeable in so simple a manner that addresses of different banks are arranged continuous to each other or addresses whose row addresses are the same in the same bank are arranged continuous to each other, under a condition where a plurality of processes or a plurality of processors access without any break, this configuration may permit only a particular process or processor to access data but may delay accesses by other processes or processors until later, which in turn stagnates the other processes or processing at the other processors. Describing the reason, in a process or processor for processing an image or the like, data whose row addresses are the same in the same bank but whose column addresses alone are different are often accessed continuously. In such a case, even if an access to an address of a different bank or a different row address by other process or processor is inserted, the inserted access is deferred until later because of a change in the access order in accordance with the condition described above.
Further, if an access order for accessing addresses is changed simply to shorten an access time, chances are that certain accesses will be always delayed until later. This occurs when accesses which are added later are always preferable to shorten an access time. This can be avoided if priority ranks are set for accesses, a priority rank for an access which was delayed repeatedly is advanced and an access with a certain or higher priority rank is allowed unconditionally.